Since the development of integrated circuit ("IC") technology, computers and computer storage devices have been made from IC chips formed from wafers of semiconductor material. After a wafer is made, the chips are typically separated from each other by dicing the wafer. Thereafter, the individual chips are bonded to carriers of various types, interconnected by wires and packaged. Such "two-dimensional" packages of chips fail to optimize the number of circuits that might be fabricated in a given space, and also introduce undesirable signal delays, capacitance, and inductance as signals travel between chips.
Recently, electronic modules comprising three-important packaging approach. A typical three-dimensional electronic module consists of multiple IC chips adhesively secured together as a "stack." A metallization layer is often provided directly on a side surface of the electronic module, the side surface being defined in part by the edge surfaces of the IC chips of the stack. The side surface metallization layer interconnects the chips in the stack and facilitates electrical connection of the stack to circuitry external to the module. Specifically, the metallization layer can include both individual contacts and bus contacts.
The overall dimensions of an electronic module need to be minimized in order to fit into industry standard packages, with the smallest being the most highly valued. A typical application involves next generation memory chips (e.g., 64 million bit dynamic random access memories, i.e. "64 Mbit DRAMs") which contain four times the number of bits, with the same control functions, as the previous generation of memory chips (e.g., 16 Mbit DRAMs). This can be accomplished only when the advancement of semiconductor tools and processes allow significant (2.times.) reduction in geometries. An alternative to waiting for the requisite advances in single chip semiconductor tools and processes is to combine existing memory chips (16 Mbit) so they emulate next generation (64 Mbit) memory chips. Chip "stacking" technology provides just such a means. For example, a 64 Mbit memory chip function may be created by "stacking" four 16 Mbit memory chips and one buffer chip. However, this electronic module must fit into the space of a single 64 Mbit memory chip. Thus, dimensional minimization is important to the success of this technology. However, current "stacking" technologies fail to provide the minimization required.
The means used to interconnect the modules to external electrical circuitry effects the overall size of electronic modules. In addition to the side surface connection scheme previously mentioned, connection can be made through an end surface of an electronic module defined by a substantially planar main surface of an end semiconductor chip in the stack. Interconnection to external circuitry from an end surface of an electronic module is typically performed by the use of a "thick" ceramic end cap. The front surface of the end cap contains metallized contacts for external connection.
Ceramic end cap techniques significantly increase the size of the electronic modules. A "thick" end cap is necessary primarily due to the use of "T-connects" on the side surface of the electronic module (corresponding to the edge surface of the end cap) to reliably connect side surface metallization to back surface "transfer wiring" on the end cap. The end cap must be thick enough (i.e., the edge of the end cap must be wide enough) to accommodate the side surface T-connections. Thus, end caps increase the size of electronic modules in which they are contained.
Ceramic end caps also pose wiring density problems because they generally use thick-film wiring. The wiring ground rules for currently used thick-film wiring are much larger than those used for thin-film wiring. For long stacks, the wiring density required on the end cap could exceed the minimum wiring width and spacing for thick-film technology. While thin-film wiring could be used, the addition of thin-film wiring to "thick" end caps is costly and complex. Thus, the "thick" end cap increases the size of the module and restricts the number of IC chips it can contain.
The interconnect between IC chips and a thick ceramic end cap is complex and costly. Specifically, electrically conductive vias originating from the contacts on the front surface of the end cap are etched completely through to the back surface of the end cap. Back surface transfer metallization then extends from the vias to the edges of the end cap (corresponding to side surfaces of the module) to facilitate connection to the side surface metallization layer.
A particular set of problems is related to forming insulating layers in association with surface metallization layers on surfaces of stacks of IC chips. Current insulator layer deposition techniques for electronic modules usually involve spin applying a liquid to a stack's surface(s). This creates several problems including: large (as a percentage of the total area and film-thickness) edge effects on individual stacks and tight balancing requirements for multiple stack spinning in a single fixture. Unique and expensive fixtures to minimize edge effects and to properly balance multiple stack insulator spin application could be implemented, but this solution increases costs. These problems are exacerbated when attempting to process small stacks (herein defined as stacks of IC chips with fewer IC chips than "long" stacks).
Currently, formation of small stacks may involve the formation of a "long stack," and subsequent division thereof into multiple small stacks. This is performed at pre-defined locations within the long stack. For example, if a small stack is to include four electrically-good, burned-in memory chips and an end cap, then one must add additional IC chips in each small stack to allow for burn-in and process chip losses such that an adequate yield of four good IC chips within the small stack is ensured. Thus, each small stack within the long stack may consist of, for example, six memory chips and an end cap. Segmentation of the long stack into small stacks is therefore performed between the end cap of one small stack and the first chip of a next small stack.
Clearly, the current long stack/small stack structure has several limitations associated therewith. Referring to the small stack including four primary memory chips and two "spare" memory chips, if the "spare" chips are not needed then the small stack includes two electrically-good, burned-in chips that are never used. Moreover, inclusion of "spare" chips detrimentally increases the overall size of the electronic module. Similarly, if burn-in and cube processing result in less than four good chips in a small stack, the entire small stack is discarded. Thus, the remaining electrically-good, burned-in chips (between 0 and 3) are lost. In total, the current technique of segmenting a long stack at predefined segmentation points results in unnecessary loss of electrically-good, burned-in chips, with all the commensurate impacts on product cost.
The present invention is directed towards solving all the above noted problems.